In typical Flash EPROM technology, a semiconductor wafer is processed to have a central area of a desired number of Flash EPROM transistors. Usually, surrounding the Flash EPROM transistors in a border-like arrangement are a desired number of peripheral transistors. Together, the central Flash EPROM transistors and the peripheral transistors form a non-volatile memory circuit.
Presently, scaling down of Flash EPROM cells has been considered critical in continuing the trend toward higher device density. Typically, however, the scaling of cell size has not been accompanied by a scaling in the internal operation voltage requirement for the cell. Without a corresponding reduction in voltage requirements, more severe requirements are placed on the periphery transistor devices, thus limiting the amount of die size reduction possible in Flash EPROM manufacturing.
Further, with the burden placed on the periphery transistor devices to handle high field threshold voltages, the ability to reduce the size of these periphery transistors is limited. Typically, peripheral transistors have a thick field oxide layer, on the order of 4000 angstroms (.ANG.), in order to handle these high field threshold voltages. Unfortunately, such large thicknesses in the field oxide layer contradict the desired thinness in the gate oxide layer as the device size shrinks. Thus, the ability to reduce the size of the peripheral transistors is limited by the need to maintain a thick field oxide layer in order to properly handle high field threshold voltages (e.g., on the order of .vertline..+-.12.vertline. volts (V)).
What is needed therefore is a non-volatile memory circuit structure that allows the size of peripheral transistors to be reduced without harming the ability to handle high field threshold voltages.